1. Field of the Invention
The field of the invention is data processing, or, more specifically, methods, apparatus, and products for scan verification for a device under test (‘DUT’).
2. Description of Related Art
In developing digital integrated circuits, it is desirable to test the design of a digital integrated circuit before manufacturing. The evaluation of the reliability and quality of a digital integrated circuit is commonly called “testing”, yet it is comprised of distinct phases. Functional verification is the initial phase in which designs are “tested” to ensure that they match their functional specification, that is, to verify the correctness of the design. Verification checks that all design rules are adhered to, from layout to electrical parameters; more generally, this type of functional testing checks that the circuit: (a) implements what it is supposed to do and (b) does not do what it is not supposed to do. This type of evaluation is done at the design stage and uses a variety of techniques, including logic verification with the use of hardware description languages, full functional simulation, and generation of functional test patterns.
Manufacturing testing correctly refers to the phase when one must ensure that only defect-free production chips are packaged and shipped, during which faults arising from manufacturing and/or wear-out are detected. One of the initial testing methods involved using patterns to provide instructions to the device input pins and to predict the states of the output pins. However, the density of circuitry continues to increase, while the number of I/O pins remains small. This causes a serious escalation of complexity, and testing is becoming one of the major costs to industry.
Most testing techniques are designed to be applied to combinatorial circuits only. While this may appear a strong restriction, in practice it is a realistic assumption based on the idea of designing a sequential circuit by partitioning the memory elements from the control functionality, such that the circuit can be reconfigured as combinatorial at testing time. This general approach is one of the methods in design for testability (‘DFT’). DFT encompasses any design strategy aimed at enhancing the testability of a circuit. In particular, scan design is the best known implementation for separating the latches from the combinational gates, such that some of the latches can also be reconfigured and used as either tester units or as input generator units. Scan design effectively converts sequential logic design into combinatorial logic design by connecting the elements of the circuit to shift registers. Scanning makes it possible to assure the detection of all faults in the manufactured circuit, reduce testing design time and costs, and reduce the execution time of performing tests on fabricated chips.
Scan design aims to achieve total or near total controllability and observability in sequential circuits. In this approach engineers design the elements in the scan chain (flip-flops, latches, or both) to operate either in normal mode or serial (test) mode. In the normal, or system, mode, the elements are configured for parallel operation. In test mode, the elements are loaded (controlled) by scanning in the desired data. In a similar fashion, engineers observe the data present in the elements by scanning out their contents in the serial test mode. Scan design also aids the initial bringup of the DUT in the lab using JTAG. During the debug process in the lab, if needed, scan chains aid in reconfiguring the flip-flops and latches to different values and for running tests on the DUT.
Scanning is carried out by serially injecting signals into the scan chain through device pins by enabling the scan mode on the elements in the scan chain and clocking data in thereby shifting the serial shift register and forcing data in the last elements of the scan chain to output. The phrases “scanning in” and “scanning out” emphasize different aspects of the same process. Scanning in data always entails scanning out data and vice versa.
Because scanning is such a useful process, it is important that it functions properly. Often, design of scan chains must be performed manually, which is error-prone. Thus, the design of the scanning process is verified during the initial stages of testing. The initial stages of testing, known as verification, may encompass several steps. In one of these steps, the scan verification is accomplished by simulating the device under test (‘DUT’) in a simulation and performing simulated scan operations for each scan chain. In the past, these simulated scan operations were performed by scanning in a test pattern through the entire scan chain, scanning out the contents of the scan chain, and verifying the correctness of the outputs for a given test pattern. A typical scan chain may contain 15-20,000 elements and perhaps as many as 90,000 elements. Each DUT may contain many scan chains. Although this method is thorough, simulating the scan operation in this manner can take hours. Furthermore, the important property that while scanning the scan chains other parts of the processor remain unchanged can be addressed by formal verification, which causes significant runtime drawbacks due to state explosion, or by checking all the latches surrounding the scan chain after each simulator cycle, which is also time-consuming.